Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
Table 3.4 LAN Port 0(External MII) Pins (continued)
BUFFER
TYPE
PIN
NAME
SYMBOL
DESCRIPTION
MII Receive
Data Valid
RXDV
IS/O8
(PD)
Note 3.3
MII Receive Data Valid: Indicates valid data on
RXD[3:0].
In MAC mode, this signal is input from an
11
external PHY.
In PHY mode, this signal is output to an external
MAC. See Note 3.3.
MII Receive
Clock
RXCLK
IS/O12
(PD)
MII Receive Clock:
Note 3.3 In MAC mode, this is the receiver clock input from
an external PHY.
10
In PHY mode, this is the receiver clock output to
an external MAC. See Note 3.3.
MII
Management
Data
MDIO
IS/O8
Note 3.5
MII Management Data:
In SMI/MII slave management modes, this signal
is the management data to/from an external
master.
12
In MII master management modes, this signal is
the management data to/from an external PHY.
See Note 3.5
MII
MDC
IS/O8
Note 3.6
MII Management Clock:
Management
Clock
In SMI/MII slave management modes, this is the
management clock input from an external master.
15
In MII master management modes, this is the
management clock output to an external PHY.
See Note 3.6.
MII Port
Duplex
MII_DUPLEX
IS
(PU)
Note 3.7
MII Port Duplex: This pin sets the duplex of the
MII port. Its’ value can be changed at any time (live
value) and can be overridden by disabling the
Auto-Negotiation (VPHY_AN) bit in the Virtual PHY
Basic Control Register (VPHY_BASIC_CTRL) of
the Virtual PHY.
In MAC mode, this signal is typically tied to the
duplex indication from the external PHY.
60
In PHY mode, this signal is typically tied high or low
as needed.
The polarity of this signal depends upon the
duplex_pol_strap_mii strap. If duplex_pol_strap_mii
is 0, a MII_DULPEX value of 0 indicates full duplex,
and 1 indicates half duplex. If duplex_pol_strap_mii
is 1, a MII_DULPEX value of 1 indicates full duplex,
and 0 indicates half duplex.
Note 3.3 When used as an output, the pin(s) input buffer(s) and pull-down(s) are disabled.
Revision 1.2 (04-08-08)
SMSC LAN9313/LAN9313i
DATA3S2HEET