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LAN9313I 参数 Datasheet PDF下载

LAN9313I图片预览
型号: LAN9313I
PDF下载: 下载PDF文件 查看货源
内容描述: 三端口10/100管理型以太网交换机MII [Three Port 10/100 Managed Ethernet Switch with MII]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 398 页 / 4083 K
品牌: SMSC [ SMSC CORPORATION ]
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Three Port 10/100 Managed Ethernet Switch with MII  
Datasheet  
Table 3.5 Dedicated Configuration Strap Pins (continued)  
BUFFER  
TYPE  
PIN  
NAME  
SYMBOL  
DESCRIPTION  
Port 0  
FD_FC_MII  
IS  
(PU)  
Note 3.8  
Port 0(External MII) Full-Duplex Flow Control  
Enable Strap: Configures the default of the  
TX_FC_MII and RX_FC_MII bits in the Port  
0(External MII) Manual Flow Control Register  
(MANUAL_FC_MII). When latched low, flow control  
is disabled on RX/TX. When latched high, flow  
control is enabled on RX/TX. See Note 3.9.  
(External MII)  
Full-Duplex  
Flow Control  
Enable Strap  
30  
MANUAL_FC_MII  
Port 0  
IS  
(PU)  
Note 3.8  
Port 0(External MII) Manual Flow Control Enable  
Strap: Configures the default value of the  
MANUAL_FC_MII bit in the Port 0(External MII)  
Manual Flow Control Register (MANUAL_FC_MII).  
When latched low, flow control is determined by  
Virtual Auto-Negotiation. When latched high, flow  
control is determined by TX_FC_MII and  
(External MII)  
Manual Flow  
Control  
Enable Strap  
29  
RX_FC_MII bits in the Port 0(External MII) Manual  
Flow Control Register (MANUAL_FC_MII). See  
Note 3.9, and Note 3.10.  
MNGT_MODE[1:0]  
Serial  
Management  
Mode Strap  
IS  
(PU)  
Note 3.8  
Serial Management Mode Strap: Configures the  
serial management mode.  
00 = Unmanaged mode  
01 = SMI Managed Mode  
10 = I2C Managed Mode  
11 = SPI Managed Mode  
26,28  
See Note 3.9.  
MII Mode  
Strap  
MII_MODE  
IS  
(PU)  
Note 3.8  
MII Mode Strap: Configures the mode of the  
external MII port.  
25  
0 = MAC Mode  
1 = PHY Mode  
See Note 3.9.  
PHY_ADDR_SEL  
PHY Address  
Strap  
IS  
(PU)  
Note 3.8  
PHY Address Strap: Configures the default MII  
management address values for the PHYs (Virtual,  
Port 1, and Port 2) as detailed in Section 7.1.1,  
"PHY Addressing," on page 84.  
95  
0
1
0
1
1
2
2
3
See Note 3.9.  
Note: For more information on configuration straps, refer to Section 4.2.4, "Configuration Straps," on  
page 45. Additional strap pins, which share functionality with the EEPROM pins, are described  
in Table 3.6.  
Note 3.8 This signal is pulled high through an internal pull-up resistor at all times.  
Revision 1.2 (04-08-08)  
SMSC LAN9313/LAN9313i  
DATA3S6HEET  
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