Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
Note 3.4 When used as an output, the pin input buffer and pull-up are disabled.
Note 3.5 An external pull-up is required when the SMI or MII management interface is used. This
ensures that the IDLE state of the MDIO signal is logic 1. An external pull-up is
recommended when the SMI or MII management interface is not used to avoid a floating
signal.
Note 3.6 When used as an output, the pin input buffer is disabled. An external pull-down is
recommended when the SMI or MII management interface is not used to avoid a floating
signal.
Note 3.7 This signal is pulled high through an internal pull-up resistor at all times.
Table 3.5 Dedicated Configuration Strap Pins
BUFFER
PIN
NAME
SYMBOL
TYPE
DESCRIPTION
LED Enable
Strap
LED_EN
IS
(PU)
Note 3.8
LED Enable Strap: Configures the default value
for the LED_EN bits in the LED Configuration
Register (LED_CFG). When latched low, all 8
LED/GPIO pins are configured as GPIOs. When
latched high, all 8 LED/GPIO pins are configured
as LEDs. See Note 3.9.
44
LED Function
Strap
LED_FUN[1:0]
IS
(PU)
Note 3.8
LED Function Straps: Configures the default
value for the LED_FUN bits in the LED
Configuration Register (LED_CFG). When latched
low, the corresponding bit will be cleared. When
latched high, the corresponding bit will be set. See
Note 3.9.
45,47
56
AUTO_MDIX_1
AUTO_NEG_1
Port 1 Auto-
MDIX Enable
Strap
IS
(PU)
Note 3.8
Port 1 Auto-MDIX Enable Strap: Configures the
default value for the Auto-MDIX functionality on
Port 1. When latched low, Auto-MDIX is disabled.
When latched high, Auto-MDIX is enabled. See
Note 3.9.
Port 1 Auto
Negotiation
Enable Strap
IS
(PU)
Note 3.8
Port 1 Auto Negotiation Enable Strap:
Configures the default value for the Auto-
Negotiation (PHY_AN) enable bit in the
PHY_BASIC_CTRL_1 register (See
Section 13.2.2.1). When latched low, auto-
negotiation is disabled. When latched high, auto-
negotiation is enabled.
55
53
See Note 3.9.
Port 1 Speed
Select Strap
SPEED_1
IS
(PU)
Note 3.8
Port 1 Speed Select Strap: Configures the default
value for the Speed Select LSB
(PHY_SPEED_SEL_LSB) bit in the
PHY_BASIC_CTRL_1 register (See
Section 13.2.2.1). When latched low, 10 Mbps is
selected. When latched high, 100 Mbps is selected.
See Note 3.9.
Port 1 Duplex
Select Strap
DUPLEX_1
BP_EN_1
IS
(PU)
Note 3.8
Port 1 Duplex Select Strap: Configures the
default value for the Duplex Mode (PHY_DUPLEX)
bit in the PHY_BASIC_CTRL_1 register (See
Section 13.2.2.1). When latched low, half-duplex is
selected. When latched high, full-duplex is
selected. See Note 3.9.
52
51
Port 1
Backpressure
Enable Strap
IS
(PU)
Note 3.8
Port 1 Backpressure Enable Strap: Configures
the default value for the Port 1 Backpressure
Enable (BP_EN_1) bit of the Port 1 Manual Flow
Control Register (MANUAL_FC_1). When latched
low, backpressure is disabled. When latched high,
backpressure is enabled. See Note 3.9.
SMSC LAN9313/LAN9313i
Revision 1.2 (04-08-08)
DATA3S3HEET
SMSC [ SMSC CORPORATION ]
