High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 4.1 Reset Sources and Affected LAN9312 Circuitry
RESET SOURCE
POR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
nRST Pin
Digital Reset
Soft Reset
X
X
Note 4.1
Port 2 PHY
Port 1 PHY
Virtual PHY
X
X
X
Note 4.1 In the case of a soft reset, the EEPROM Loader is run, but loads only the MAC address
into the Host MAC. No other values are loaded by the EEPROM Loader in this case.
4.2.1
Chip-Level Resets
A chip-level reset event activates all internal resets, effectively resetting the entire LAN9312.
Configuration straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A
chip-level reset is initiated by assertion of any of the following input events:
Power-On Reset (POR)
nRST Pin Reset
Chip-level reset completion/configuration can be determined by polling the READY bit of the Hardware
Configuration Register (HW_CFG) or Power Management Control Register (PMT_CTRL) until it is set.
When set, the READY bit indicates that the reset has completed and the device is ready to be
accessed.
With the exception of the Hardware Configuration Register (HW_CFG), Power Management Control
Register (PMT_CTRL), Byte Order Test Register (BYTE_TEST), and Reset Control Register
(RESET_CTL), read access to any internal resources is forbidden while the READY bit is cleared.
Writes to any address are invalid until the READY bit is set.
Note: The LAN9312 must be read at least once after any chip-level reset to ensure that write
operations function properly.
4.2.1.1
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the LAN9312, or if the power is removed
and reapplied to the LAN9312. This event resets all circuitry within the device. Configuration straps
are latched, and the EEPROM Loader is run as a result of this reset.
SMSC LAN9312
Revision 1.2 (04-08-08)
DATA3S7HEET
SMSC [ SMSC CORPORATION ]
