and the Status register, Input Data register, and
Output Data register. Table 56 shows how the
KEYBOARD AND RTC ISA INTERFACE
interface decodes the control signals.
addition to the above signals, the host interface
includes keyboard and mouse IRQs.
In
The FDC37C93xFR ISA interface is functionally
compatible with the 8042-style host interface. It
consists of the D0-7 data bus, the nIOR, nIOW
Table 56 - ISA I/O Address Map
Addresses 0x60, 0x64, 0x70 and 0x71 are qualified by AEN
ISA ADDRESS*
0x70 (R/W)
0x71 (R/W)
BLOCK
RTC
FUNCTION
Address Register
RTC
Data Register
*Bank 0 is at 70h. Bank 1 and 2 are relocatable
via the RTC Mode Register and the
Secondary Base Address for RTC Bank 1 and 2
(CR62 and CR63). See Configuration section.
ISA ADDRESS
nIOW
nIOR
BLOCK
FUNCTION*
Keyboard Data Write (C/D=0)
Keyboard Data Read
0x60
0
1
0
1
1
0
1
0
KDATA
KDATA
KDCTL
KDCTL
0x64
Keyboard Command Write (C/D=1)
Keyboard Status Read
*These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data
Read.
Keyboard Data Write
Keyboard Command Write
This is an 8 bit write only register. When
written, the C/D status bit of the status register
is cleared to zero and the IBF bit is set.
This is an 8 bit write only register. When
written, the C/D status bit of the status register
is set to one and the IBF bit is set.
Keyboard Data Read
Keyboard Status Read
This is an 8 bit read only register. If enabled by
"ENABLE FLAGS", when read, the KIRQ output
is cleared and the OBF flag in the status register
is cleared. If not enabled, the KIRQ and/or
AUXOBF1 must be cleared in software.
This is an 8 bit read only register. Refer to the
description of the Status Register for more
information.
RTC Address Register
Writing to this register sets the CMOS address
that will be read or written.
135
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