When = (1,0) bit 0 is cleared on the first write of
the Write EEPROM Data register. This status
indicates that the serial device controller has
received one byte (LSB) and is waiting for the
second byte (MSB).
BIT 4
This selects the type of EEPROM connected to
the FDC37C93xFR. If cleared, the device must
be either a 93C06 or 93C46 and if set the device
must be either an 93C56 or 93C66. This bit
must be properly set before attempting to
access the serial EEPROM.
When = (0,0) bit 1 is cleared on the second
write of the Write EEPROM Data register
indicating that two bytes have been accepted
and that the serial device interface is busy
writing the word to the EEPROM.
BIT 7-5
Reserved, set to “0”.
SERIAL EEPROM POINTER REGISTER, 0XF2
BIT 6-2
Reserved, set to “0”.
BIT 7-0
Use this register to set the serial EEPROM's
BIT 7
pointer.
The value in this register always
This bit is cleared to configure the EEPROM
interface for read operations. Clearing this bit
enables the serial EEPROM prefetch when the
Serial EEPROM Pointer Register is updated
(written or auto-incremented).
reflects the current EEPROM pointer address.
The Serial Device Pointer increments after each
pair of reads from the Resource Data register or
after each pair of writes to the Program
Resource Data register.
This bit is set to configure the EEPROM
interface for write operations. Setting this bit
disables the serial EEPROM prefetch when the
Serial EEPROM Pointer Register is updated
(written or auto-incremented).
WRITE EEPROM DATA REGISTER, 0XF3
BIT 7-0
This register allows the host to write data into
the serial EEPROM.
supports serial EEPROMS
The FDC37C93xFR
with x16
Read EEPROM Data Register, 0xF5
configurations. Two bytes must be written to
this register in order to generate an EEPROM
write cycle. The LSB leads the MSB. The first
write to this register resets bit 0 of the Write
Status register. The second write resets bit 1 of
the Write Status register and generates a write
cycle to the serial EEPROM. The Write Status
register must be polled before performing a pair
of writes to this register.
BIT 7-0
This register allows the host to read data from
the serial EEPROM. Data is not valid in this
register until bit 0 of the Read Status Register is
set. Since the EEPROM is a 16-bit device, this
register presents the LSB followed by the MSB
for each pair of register reads. Immediately after
the MSB is read, bit 0 of the Read Status
Register will be cleared, then the Serial
EEPROM Pointer Register will be auto-
incremented, then the next word of EEPROM
data will be fetched, followed by the Read
Status Register, bit 0 being set.
WRITE STATUS REGISTER, 0XF4
BIT 1 and 0
When = (1,1) Indicates that the Write EEPROM
Data register is ready to accept a pair of bytes.
132
SMSC [ SMSC CORPORATION ]
