The polarity of nIDE2_OE, which is normally
active low, is programmable through a bit in the
GP20 Configuration Register.
GP16 Joystick Function
The FDC37C93xFR may be configured to
generate either a Joystick Chip Select or a
Joystick Read Strobe on GP16. The polarity is
programmable through a bit in the GP16
configuration register. When configured as a
Joystick Chip Select the output is simply a
decode of the address = 0x201 qualified by AEN
active. When configured as a Joystick Read
Strobe the output is a decode of the address =
0x201 qualified by IOR and AEN both active.
The Joystick Chip Select or Read Strobe is
normally active low, however, its polarity is
programmable through a bit in the GP20
Configuration Register.
SERIAL EEPROM INTERFACE
Four of the FDC37C93xFR's general purpose
I/O pins may be configured to provide a four
wire direct interface to a family of industry
standard serial EEPROMs.
For proper
operation the polarity bits of these four pins
must be set to 0 (non-inverting). The interface
is depicted below and will allow connection to
either a 93C06 (256-bit), a 93C46 (1K-bit), a
93C56 (2K-bit), or a 93C66 (4K-bit) device.
GP21 <---- Serial EEPROM Data In
GP22 ----> Serial EEPROM Data Out
GP23 ----> Serial EEPROM Clock
GP24 ----> Serial EEPROM Enable
GP17 JOYSTICK FUNCTION
The FDC37C93xFR may be configured to
generate a Joystick Write Strobe on GP17.
When configured as a Joystick Write Strobe the
output is a decode of the address = 0x201
qualified by IOW and AEN both active.
Reset out is an internal signal from the keyboard
controller (Port 20). The FDC37C93xFR may be
configured to drive this signal onto GP20 by
programming its GPI/O configuration register.
Access to the serial EEPROM is only available
when the FDC37C93xFR is in the configuration
mode. A set of six configuration registers,
located in Logical Device 6 (RTC) is used to
fully access and configure the serial EEPROM.
The registers are defined as follows:
The Joystick Write Strobe is normally active
low, however, its polarity is programmable
through
a bit in the GP20 Configuration
Register.
IDE2 BUFFER ENABLE/RESET OUT
The FDC37C93xFR may be configured to
provide an nIDE2_OE buffer enable signal on
pin GP20. The IDE2 Mode Register (0xF0 of
SERIAL EEPROM MODE REGISTER, 0XF1
BIT 3-0
Logical Device 2) contains
a
bit which
These are the lock bits which once set deny
access to the serial EEPROM's first 128 bytes in
32 byte blocks. Bit 0 locks the first block, bit 1
the second block, bit 2 the third block and bit 3
the fourth block of 32 bytes. Once these lock
bits are set they cannot be reset in any way
other than by a Hard reset or a Power-on reset.
determines whether nIDE1_OE or nIDE2_OE is
active for IDE2 transfers. If GP20 is selected
as a General Purpose I/O pin, IDE2 I/O
accesses must be configured to activate
nIDE1_OE for IDE2 transfers if a secondary
hard drive interface is present.
131
SMSC [ SMSC CORPORATION ]
