effect. When a GPI/O port is programmed as
an output, the logic value written into the GPI/O
register is either output to or inverted to the
GPI/O pin; when read the result will reflect the
contents of the GPI/O register bit. This is
summarized in Table 53.
Reading and Writing GPI/O Ports
When a GPI/O port is programmed as an input,
reading it through the GPI/O register latches
either the inverted or non-inverted logic value
present at the GPI/O pin; writing it has no
Table 53 - GPI/O Read/Write Behavior
GPI/O INPUT PORT
HOST OPERATION
GPI/O OUTPUT PORT
bit value in GP register
bit placed in GP register
Read
Write
latched value of GPI/O pin
no effect
WATCH DOG TIMER/POWER LED CONTROL
Pins 30 (nIOROP/GP46) and 111 (RD0/GP60)
BASIC FUNCTIONS
can also be configured for Power LED.
The FDC37C93xFR contains a Watch Dog
Timer (WDT) and also has the capability to
directly drive the system's Power-on LED.
WATCH DOG TIMER
The FDC37C93xFR's WDT has a programmable
time-out ranging from one to 255 minutes with
one minute resolution, or one to 255 seconds
with one second resolution. The units of the
WDT timeout value are selected via bit[7] of the
GPA_GPW_EN register (located at 0xF1 of
Logical Device 8). The WDT time-out value is
set through the WDT_VAL Configuration
register. Setting the WDT_VAL register to 0x00
disables the WDT function (this is its power on
default). Setting the WDT_VAL to any other
non-zero value will cause the WDT to reload
and begin counting down from the value loaded.
When the WDT count value reaches zero the
counter stops and sets the Watchdog time-out
status bit in the WDT_CTRL Configuration
Register. Note: Regardless of the current state
of the WDT, the WDT time-out status bit can be
directly set or cleared by the Host CPU.
The Watch Dog time-out status bit (WDT_CTRL
bit-0) is mapped to GP12 when the alternate
function bit of the GP12 Configuration Register
is set "and" bit 6 of the IR Options Register = 0.
In addition, the Watch Dog time-out status bit
may be mapped to an interrupt through the
WDT_CFG Configuration Register.
Pins 30 (nIOROP/GP46) and 112 (RD1/GP61)
can also be configured for WDT.
GP13 may be configured as a high current LED
driver to drive the power LED.
This is
accomplished by setting the alternate function
bit of the GP13 Configuration Register "and"
clearing bit 6 of the IR Options Register.
The infrared signals, IRRX and IRTX, are
mapped to GP12 and GP13 when the alternate
function bit of the GP12 and GP13
Configuration Registers is set "and" bit-6 of the
IR Options Register is set.
There are three system events which can reset
the WDT, these are a Keyboard Interrupt, a
Mouse Interrupt, or I/O reads/writes to address
0x201 (the internal or an external Joystick Port).
128
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