Table 55 - Watchdog Timer/Power LED Configuration Registers
CONFIG REG.
WDT_VAL
BIT FIELD
Bits 7:0
DESCRIPTION
Binary coded time-out value, 0x00 disables the WDT
Joystick enable
WDT_CFG
Bit 0
Bit 1
Keyboard enable
Bit 2
Mouse enable
Bit 3
Power LED toggle on WDT time-out
Bits 7:4
WDT interrupt mapping,
0000b = diables IRQ mapping
WDT_CTRL
Bit 0
WDT time-out status bit
Power LED toggle
Bit 1
Bit 2
Force Timeout, self-clearing
P20 Force Timeout Enable
Reserved, set to zero
Bit 3
Bit 4
Bit 5,6,7
Stop_Cnt, Restart_Cnt, SPOFF: used for soft power
management
GENERAL PURPOSE ADDRESS DECODER
GENERAL PURPOSE WRITE
General Purpose I/O pin GP15 may be
configured as a General Purpose Write pin. The
General Purpose Write provides an output
decoded from the 12-bit address stored in a
two-byte Base I/O Address Register (Logical
Device 8 Configuration Registers 0x62, 0x63)
qualified with IOW and AEN. This General
General Purpose I/O pin GP14 may be
configured as a General Purpose Address
Decode Pin. The General Purpose Address
Decoder provides an output decoded from bits
A11-A1 of the 12-bit address stored in a two-
byte Base I/O Address Register (Logical Device
8 Configuration Registers 0x60, 0x61) qualified
with AEN. Thus, the decoder provides a two
address decode where A0=X. This General
Purpose output is normally active low, however
the polarity may be altered through the polarity
bit in its GPI/O Configuration Register.
Purpose output is
normally
active
low,
however the polarity may be altered through the
polarity bit in its GPI/O Configuration Register.
The GPA_GPW_EN Configuration Register
contains two bits which allow the General
Purpose Address Decode and Write functions to
be independently enabled or disabled.
The pins nHDCS0 and nHDCS1 can also be
used as general purpose address decoders. See
Configuration section, Logical Device 1, for
more information.
JOYSTICK CONTROL
The Base I/O address of the Joystick (Game)
Port is fixed at address 0x201.
130
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