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FDC37CXFR 参数 Datasheet PDF下载

FDC37CXFR图片预览
型号: FDC37CXFR
PDF下载: 下载PDF文件 查看货源
内容描述: 即插即用兼容超I / O控制器,提供快速IR [Plug and Play Compatible Ultra I/O Controller with Fast IR]
分类和应用: 控制器
文件页数/大小: 258 页 / 898 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号FDC37CXFR的Datasheet PDF文件第125页浏览型号FDC37CXFR的Datasheet PDF文件第126页浏览型号FDC37CXFR的Datasheet PDF文件第127页浏览型号FDC37CXFR的Datasheet PDF文件第128页浏览型号FDC37CXFR的Datasheet PDF文件第130页浏览型号FDC37CXFR的Datasheet PDF文件第131页浏览型号FDC37CXFR的Datasheet PDF文件第132页浏览型号FDC37CXFR的Datasheet PDF文件第133页  
The effect on the WDT for each of these system  
events may be individually enabled or disabled  
through bits in the WDT_CFG configuration  
register. When a system event is enabled  
through the WDT_CFG register, the occurrence  
of that event will cause the WDT to reload the  
value stored in WDT_VAL and reset the WDT  
time-out status bit if set. If all three system  
events are disabled the WDT will inevitably time  
out.  
The host may force a Watch Dog time-out to  
occur by writing a "1" to bit 2 of the WDT_CTRL  
(Force WD Time-out) Configuration Register.  
Writing a "1" to this bit forces the WDT count  
value to zero and sets bit 0 of the WDT_CTRL  
(Watch Dog Status). Bit 2 of the WDT_CTRL is  
self-clearing.  
Power LED Toggle  
Setting bit 1 of the WDT_CTRL Configuration  
Register will cause the power LED output driver  
to toggle at 1 Hertz with a 50 percent duty cycle.  
When this bit is cleared the Power LED output  
will drive continuously unless it has been  
configured to toggle on Watch Dog time-out  
conditions. Setting bit 3 of the WDT_CFG  
Configuration Register will cause the Power LED  
output driver to toggle at 1 Hertz with a 50  
percent duty cycle whenever the WDT time-out  
status bit is set. The truth table below clarifies  
the conditions for which the power LED will  
toggle.  
The Watch Dog Timer may be configured to  
generate an interrupt on the rising edge of the  
time-out status bit.  
mapped to an interrupt channel through the  
WDT_CFG Configuration Register. When  
The WDT interrupt is  
mapped to an interrupt the interrupt request pin  
reflects the value of the WDT time-out status bit.  
When the polarity bit is 0, GP12 reflect the value  
of the Watch Dog Time-out status bit, however,  
when the polarity bit is 1, GP12 reflects the  
inverted value of the Watch Dog Time-out status  
bit. This is also true for the other two pins used  
for WDT; nIOROP (GP46) and RD1 (GP61).  
When the polarity bit is 0, the power LED output  
asserts or drives low. If the polarity bit is 1 then  
the power LED output asserts or drives high.  
Table 54 - LED Toggle Truth Table  
WDT_CFG BIT 3  
POWER LED  
WDT_CTRL BIT 1  
WDT_CTRL BIT 0  
POWER LED TOGGLE  
TOGGLE ON WDT  
POWER LED STATE  
Toggle  
WDT T/O STATUS BIT  
1
0
0
0
X
0
1
1
X
X
0
1
Continuous  
Continuous  
Toggle  
129  
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