In addition, the GPI/O port may be optionally
programmed to steer its signal to a Combined
General Purpose Interrupt request output pin on
the FDC37C93xFR. The interrupt channel for the
Combined Interrupt is selected by the GP_INT
General Purpose I/O Configuration Registers
Assigned to each GPI/O port is an 8-bit GPI/O
Configuration Register which is used to
independently program each I/O port. The
GPI/O Configuration Registers are only
accessible when the FDC37C93xFR is in the
Configuration Mode; more information can be
found in the Configuration section of this
specification.
Configuration
Register
defined
in
the
FDC37C93xFR System Configuration Section.
The Combined Interrupt is the "ORed" function
of the interrupt enabled GPI/O ports and will
represent a standard ISA interrupt (edge high).
Each GPI/O port may be programmed as either
a simple inverting or non-inverting input or
output port, or as an alternate function port. The
least-significant four bits of each GPI/O
Configuration Register define the operation of
the respective GPI/O port. The basic GPI/O
operations are outlined in Table 52.
When programmed as an input steered onto
the General Purpose Combined Interrupt (GP
IRQ), the Interrupt Circuitry contains
a
selectable debounce/digital filter circuit in
order that switches or push-buttons may be
directly connected to the chip. This filter will
reject signals with pulse widths of 1ms or less.
Table 52 - GPI/O Configuration Register Bits [3:0]
ALT FUNC
BIT 3
INT EN
BIT 2
POLARITY
BIT 1
I/O
BIT 0
0=DISABLE 0=DISABLE
0=NO INVERT
1=INVERT
1=INPUT
0=OUTPUT
GPI/O PORT
OPERATION
1=SELECT
1=ENABLE
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Simple non-inverting output
Simple non-inverting input
Simple inverting output
Simple inverting input
Non-inverting output steered back
to GP IRQ
0
0
0
1
1
1
0
1
1
1
0
1
Non-inverting input steered to GP
IRQ
Inverting output steered back to
GP IRQ
Inverting input steered to GP IRQ
125
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