IRQSER CYCLE MODES
There are two modes of operation for IRQSER cycles: Quiet (Active) Mode and Continuous (Idle) Mode. In Quiet
Mode any device may initiate an IRQSER cycle. In Continuous Mode only the host controller can initiate an IRQSER
cycle (FIGURE 4).
Following a system reset the SIRQ bus defaults to Continuous Mode. IRQSER cycle mode transitions can only occur
during the Stop Frame (
FIGURE 5). Slaves must continuously sample the pulse width of the Stop Frame to determine the mode of the next
START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
SL
or
H
R
T
S
R
T
S
R
T
S
R
T
H
PCICLK
START1
IRQSER
IRQ1 Host Controller
None
IRQ1
None
Drive Source
IRQSER cycle (see the Stop Cycle Control section on page 94).
FIGURE 4 - START FRAME TIMING W/SOURCE SAMPLED LOW PULSE ON IRQ1
Notes:
H=Host Control
SL=Slave Control
R=Recovery
T=Turn-around
S=Sample
1)
2)
3)
Start Frame pulse can be 4-8 clocks wide
PCICLK = CLK33 pin (33MHz PCI Clock input)
IRQSER = SIRQ pin
IRQ14
FRAME
R
IRQ15
FRAME
R
IOCHCK#
FRAME
STOP FRAME
NEXT CYCLE
I 2
S
T
S
T
S
R
T
H
R
T
PCICLK
IRQSER
Driver
1
3
START
STOP
Host Controller
None
IRQ15
None
FIGURE 5 - STOP FRAME TIMING W/HOST USING 17 IRQSER SAMPLING PERIOD
Notes:
H=Host Control
R=Recovery
T=Turn-around
S=Sample
I= Idle
1)
2)
3)
STOP pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
There may be none, one or more Idle states during the Stop Frame.
The next IRQSER cycle’s Start Frame pulse may or may not start immediately after the
turn-around clock of the Stop Frame.
4)
5)
PCICLK = CLK33 pin (33MHz PCI Clock input)
IRQSER = SIRQ pin
Quiet (Active) Mode
In Quiet Mode any device may initiate a Start Frame by driving the IRQSER low for one clock while the IRQSER is
Idle (FIGURE 4). After driving low for one clock, slaves must immediately tristate IRQSER without at any time driving
high.
A Start Frame may not be initiated while the IRQSER is Active. The IRQSER is Idle between Stop and Start Frames.
The IRQSER is Active between Start and Stop Frames. Quiet Mode operation allows the IRQSER to be idle when
there are no IRQ/Data transitions.
SMSC DS – FDC37N3869
Page 92
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
