Model 30 Interface Mode
Table 28 - DIR Model 30 Interface Mode
7
6
0
5
0
4
0
3
2
1
0
DSK CHG
DMAEN
NOPREC
DRATE
SEL1
DRATE
SEL0
RESET
N/A
0
0
0
0
0
1
0
CONDITION
Data Rate Select, Bits 0 - 1
These bits control the data rate of the floppy controller. See Table 22 for the settings corresponding to the individual
data rates. The data rate select bits are unaffected by a software reset, and are set to 250kb/s after a hardware
reset.
Noprec, Bit 2
This bit reflects the value of the NOPREC bit set in the CCR register.
DMAEN, Bit 3
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
Undefined, Bits 4 - 6
Always read as a logic “0”
DSK CHG, Bit 7
The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the pin. The DSK CHG
bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on
page 107).
CONFIGURATION CONTROL REGISTER (CCR)
The Configuration Control Register (Bass Address + 7: Write-only) is write-only in all modes. Table 29 shows the
CCR in PC/AT mode and PS/2 mode. Table 30 shows the CCR in Model 30 mode.
PC/AT and PS/2 Interface Modes
Table 29 - CCR PC/AT and PS/2 Interface Modes
7
6
5
4
3
2
1
0
DRATE
SEL1
DRATE
SEL0
RESET
N/A
N/A
N/A
N/A
N/A
N/A
1
0
CONDITION
Data Rate Select, Bits 0 - 1
These bits determine the data rate of the floppy controller. See Table 22 for the appropriate values.
Reserved, Bits 2 - 7
Bits 2 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read.
Model 30 Interface Mode
Table 30 - CCR Model 30 Interface Mode
7
6
5
4
3
2
1
0
NOPREC
DRATE
SEL1
DRATE
SEL0
RESET
N/A
N/A
N/A
N/A
N/A
N/A
1
0
CONDITION
SMSC DS – FDC37N769
Page 28 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
