the command unless an illegal command condition is detected. After the last parameter byte is received, RQM
remains “0” and the FDC automatically enters the next phase as defined by the command definition.
The FIFO is disabled during the command phase to provide for the proper handling of the “Invalid Command”
condition.
Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode
as indicated in the Specify command.
After a reset, the FIFO is disabled. Each data byte is transferred by an FINT or FDRQ depending on the DMA mode.
The Configure command can enable the FIFO and set the FIFO threshold value.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> is defined
as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The
parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing
of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for
use with a “fast” system.A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency
period after a service request, but results in more frequent service requests.
Non-DMA Mode Transfers
FIFO to Host
The FINT pin and RQM bits in the Main Status Register are activated when the FIFO contains (16-<threshold>) bytes
or the last bytes of a full sector have been placed in the FIFO. The FINT pin can be used for interrupt-driven
systems, and RQM can be used for polled systems. The host must respond to the request by reading data from the
FIFO. This process is repeated until the last byte is transferred out of the FIFO. The FDC will deactivate the FINT
pin and RQM bit when the FIFO becomes empty.
Host to FIFO
The FINT pin and RQM bit in the Main Status Register are activated upon entering the execution phase of data
transfer commands. The host must respond to the request by writing data into the FIFO. The FINT pin and RQM bit
remain true until the FIFO becomes full. They are set true again when the FIFO has <threshold> bytes remaining in
the FIFO. The FINT pin will also be deactivated if TC and nDACK both go inactive. The FDC enters the result phase
after the last byte is taken by the FDC from the FIFO (i.e. FIFO empty condition).
DMA Mode Transfers
FIFO to Host
The FDC activates the DDRQ pin when the FIFO contains (16 - <threshold>) bytes, or the last byte of a full sector
transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the
FIFO. The FDC will deactivate the DDRQ pin when the FIFO becomes empty. FDRQ goes inactive after nDACK
goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present
on nDACK). A data underrun may occur if FDRQ is not removed in time to prevent an unwanted cycle.
Host to FIFO
The FDC activates the FDRQ pin when entering the execution phase of the data transfer commands. The DMA
controller must respond by activating the nDACK and nIOW pins and placing data in the FIFO. FDRQ remains active
until the FIFO becomes full. FDRQ is again set true when the FIFO has <threshold> bytes remaining in the FIFO.
The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), indicating that no more
data is required. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active
edge of nIOW of the last byte, if no edge is present on nDACK). A data overrun may occur if FDRQ is not removed in
time to prevent an unwanted cycle.
SMSC DS – FDC37N769
Page 32 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
