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FDC37N769_07 参数 Datasheet PDF下载

FDC37N769_07图片预览
型号: FDC37N769_07
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V超级I / O控制器具有红外支持针对便携式应用 [3.3V Super I/O Controller with Infrared Support for Portable Applications]
分类和应用: 控制器便携式
文件页数/大小: 137 页 / 659 K
品牌: SMSC [ SMSC CORPORATION ]
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DATA RATE SELECT REGISTER (DSR)  
The Data Rate Select Register (Base Address + 4: Write-only) is used to program the data rate, amount of write  
precompensation, power down status, and software reset (Table 20). Note: the data rate is programmed using the  
Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel applications.  
Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of  
either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which  
corresponds to the default precompensation setting and 250 Kbps.  
Table 20 - Data Rate Select Register  
7
6
5
4
3
2
1
0
S/W  
RESET  
POWER  
DOWN  
0
PRE-  
PRE-  
PRE-  
DRATE DRATE  
COMP2 COMP1 COMP0  
SEL1  
SEL0  
RESET  
0
0
0
0
0
0
1
0
CONDITION  
Data Rate Select, Bits 0 - 1  
These bits control the data rate of the floppy controller. See Table 22 for the settings corresponding to the individual  
data rates. The data rate select bits are unaffected by a software reset and are set to 250 Kbps after a hardware  
reset.  
Precompensation Select, Bits 2 - 4  
These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 21  
shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track  
number to start precompensation. The starting track number can be changed using the Configure command.  
Undefined, Bit 5  
Should be written as a logic “0”.  
Low Power, Bit 6  
A logic “1” written to this bit will put the floppy controller into Manual Low Power mode. The floppy controller clock and  
data separator circuits will be turned off. The controller will come out of manual low power mode after a software  
reset or following access to the Data Register or Main Status Register.  
Software Reset, Bit 7  
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.  
SMSC DS – FDC37N769  
Page 24 of 137  
Rev. 02-16-07  
DATASHEET  
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