Table 23 - Drive Rate Table (Recommended)
DRIVE RATE
FORMAT
(see section
DRT1
DRT0
CR0B on page 104 to program Drive Rate)
360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
3-Mode Drive
0
0
1
0
1
0
2 Meg Tape
Table 24 - Default Precompensation Delays
PRECOMPENSATION
DATA RATE
2 Mbps
DELAYS
125 ns
1 Mbps
41.67 ns
125 ns
125 ns
500 Kbps
300 Kbps
250 Kbps
125 ns
DATA REGISTER (FIFO)
The Data Register (Base Address + 5) is used to transfer all command parameter information, disk data and result
status between the host processor and the floppy disk controller. The Data Register is Read/Write. Data transfers are
governed by the RQM and DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the Configure command (enable full FIFO operation with
threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing
a
disk error. Table 25 gives several examples of service delays with a FIFO. The data is based upon the following
formula:
Threshold# × (8 ÷ Data Rate) - 1.5μS = DELAY
At the start of a command the FIFO action is always disabled and command parameters must be sent based upon the
RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure
that invalid data is not transferred.
An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the
current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so
that the result phase may be entered.
SMSC DS – FDC37N769
Page 26 of 137
Rev. 02-16-07
DATASHEET
SMSC [ SMSC CORPORATION ]
