Table 34 - Status Register 3
DESCRIPTION
BIT
NO.
7
SYMBOL
NAME
Write
Unused. This bit is always “0”.
6
WP
Indicates the status of the WP pin. The Write Protected bit also depends
upon the state of the Force Write Protect bits in the Force FDD Status
Change configuration register (see section CR17 on page 107).
Unused. This bit is always “1”.
Indicates the status of the TRK0 pin.
Unused. This bit is always “1”.
Protected
5
4
3
2
T0
Track 0
HD
Head
Indicates the status of the HDSEL pin.
Address
1,0
DS1,0
Drive
Indicates the status of the DS1, DS0 pins.
Select
Reset
There are three sources of system reset on the FDC: the RESET pin of the FDC37N769, a reset generated via a bit
in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All
resets take the FDC out of the power down state.
All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in
progress will corrupt the data and CRC.
On exiting the reset state, various internal registers are cleared, including the Configure command information, and
the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.
RESET Pin (Hardware Reset)
The RESET pin is a global reset and clears all registers except those programmed by the Specify command. The
DOR reset bit is enabled and must be cleared by the host to exit the reset state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and
the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it.
DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must
manually clear this reset bit in the DOR to exit the reset state.
DMA Transfers
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the FDRQ pin during
a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid.
Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is performed by
the FDC based only on nDACK. This mode is only available when the FDC has been configured into byte mode
(FIFO disabled) and is programmed to do a read. With the FIFO enabled, the FDC can perform the above operation
by using the new Verify command; no DMA operation is needed.
Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result.
Each phase is described in the following sections.
Command Phase
After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the
commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the
command phase is complete. (Refer to Table 36 for the command set descriptions). These bytes of data must be
transferred in the order prescribed.
Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO
must be equal to “1” and “0” respectively before command bytes may be written. RQM is set false by the FDC after
each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of
SMSC DS – FDC37N769
Page 31 of 137
Rev. 02-16-07
DATASHEET
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