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FDC37N769_07 参数 Datasheet PDF下载

FDC37N769_07图片预览
型号: FDC37N769_07
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V超级I / O控制器具有红外支持针对便携式应用 [3.3V Super I/O Controller with Infrared Support for Portable Applications]
分类和应用: 控制器便携式
文件页数/大小: 137 页 / 659 K
品牌: SMSC [ SMSC CORPORATION ]
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Table 25 - Example FIFO Service Delays  
EXAMPLE DATA RATES  
FIFO  
THRESHOLD  
EXAMPLES  
2Mbps  
1Mbps  
500Kbps  
1 byte  
1 x 4μs - 1.5μs = 2.5μs  
2 x 4μs - 1.5μs = 6.5μs  
8 x 4μs - 1.5μs = 30.5μs  
1 x 8μs - 1.5μs = 6.5μs  
2 x 8μs - 1.5μs = 14.5μs  
8 x 8μs - 1.5μs = 62.5μs  
1 x 16μs - 1.5μs = 14.5μs  
2 x 16μs - 1.5μs = 30.5μs  
8 x 16μs - 1.5μs = 126.5μs  
15 x 16μs - 1.5μs = 238.5μs  
2 bytes  
8 bytes  
15 bytes  
15 x 4μs - 1.5μs = 58.5μs 15 x 8μs - 1.5μs = 118.5μs  
DIGITAL INPUT REGISTER (DIR)  
The Digital Input Register (Bass Address + 7: Read-only) is read-only in all modes. Table 26 shows the DIR in PC/AT  
mode, Table 27 shows the DIR in PS/2 mode, and Table 28 shows the DIR in Model 30 mode.  
PC-AT Interface Mode  
Table 26 - DIR PC/AT Interface Mode  
7
6
5
4
3
2
1
0
DSK CHG  
N/A  
RESET  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
CONDITION  
Undefined, Bits 0 - 6  
The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register.  
DSK CHG, Bit 7  
The DSK CHG bit monitors the state of the pin of the same name and reflects the opposite value seen on the disk  
cable. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register  
(see section CR17 on page 107).  
PS/2 Interface Mode  
Table 27 - DIR PS/2 Interface Mode  
7
6
5
4
3
2
1
0
DSK CHG  
1
1
1
1
DRATE  
SEL1  
DRATE  
SEL0  
nHIGH  
DENS  
RESET  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
1
CONDITION  
nHIGH DENS, Bit 0  
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are  
selected.  
Data Rate Select, Bits 1 - 2  
These bits control the data rate of the floppy controller. See Table 22 for the settings corresponding to the individual  
data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware  
reset.  
Undefined, Bits 3 - 6  
Always read as a logic “1”  
DSK CHG, Bit 7  
The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. The  
DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section  
CR17 on page 107).  
SMSC DS – FDC37N769  
Page 27 of 137  
Rev. 02-16-07  
DATASHEET  
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