10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
A0-A2
VALID
t1
t2
nCS
t4
t7
t3
DIR
t5
t6
nDS
t10
t11
Note 2
t8
t9
D0-D15
VALID DATA
t12
t13
nIOCS16
VALID VALUE
CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0
min
Parameter
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
max
units
nS
nS
nS
nS
nS
15
10
5**
0
10
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
nS
nS
nS
nS
nS
nS
nS
nS
4TARB
10
*
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS Inactive
nDS Low to Valid Data
nDS High to Data High Impedence
nDS Low Width
nDS High Width
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
40**
20
0
60
20
40***
0****
*
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
**
nCS may become active after control becomes active, but the access time (t8) will
now be 45nS measured from the leading edge of nCS.
*** t12 is measured from the latest active (valid) timing among nCS, A0-A2.
****
t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 1:
Note 2:
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
SMSC COM20022I
Page 65
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
