10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
t12
t13
nIOCS16
VALID VALUE
A0-A2
VALID
t1
t2
t7
nCS
t4
t3
t5
DIR
t10
t11
nDS
Note 2
t6**
t8
t6
t9
VALID DATA
D0-D15
CASE 1: BUSTMG pin = HIGH
Parameter
t1 Address Setup to nDS Active
t2 Address Hold from nDS Inactive
t3 nCS Setup to nDS Active
t4 nCS Hold from nDS Inactive
t5 DIR Setup to nDS Active
min
15
10
5
0
max
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
10
t6 Cycle Time (nDS
to Next Time
)**
4TARB
*
t7 DIR Hold from nDS Inactive
t8 Valid Data Setup to nDS High
t9 Data Hold from nDS High
t10 nDS Low Width
10
30***
10
20
20
t11 nDS High Width
t12 nIOCS16 Output Delay from nCS Low
t13 nIOCS16 Hold Delay from nCS High
40****
0*****
*
TARB is the Arbitration Clock Period
T
T
T
ARB is identical to Topr if SLOW ARB = 0
ARB is twice Topr if SLOW ARB = 1
opr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
****: t12 is measured from the latest active (valid) timing among nCS, A0-A2.
*****:
t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
Note 1:
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to the leading edge
of the next nDS.
Write cycle for Address Pointer Low Registers occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle
SMSC COM20022I
Page 69
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
