10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
AD0-AD2,
D3-D15
VALID
VALID DATA
t1
t2,
t4
nCS
t3
t10
t9
ALE
t7
t5
nWR
t6
Note 2
t8**
t15
t8
t12
t11
Note 3
t14
nRD
t13
Previous Value
Invalid
Valid Value
nIOCS16
MUST BE: BUSTMG pin = HIGH
min
Parameter
max
units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
20
10
10
10
15
30
10
Valid Data Setup to nDS High
Data Hold from nDS High
Cycle Time (nWR
to Next
)**
4TARB*
ALE High Width
ALE Low Width
nWR Low Width
nWR High Width
20
20
20
20
20
0
nRD
to nWR Low
nIOCS16 Hold Delay from ALE Low
nIOCS16 Output Delay from ALE Low
40
*
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Note 1:
**
Note 2:
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
Note 3:
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
Revision 09-27-07
Page 62
SMSC COM20022I
DATASHEET
SMSC [ SMSC CORPORATION ]
