10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
A0-A2
VALID
t1
t2
nCS
t4
t9
t3
Note 3
t8
nRD
t10
t5
nWR
Note 2
t5**
t6
t11
t12
t7
D0-D15
VALID DATA
nIOCS16
VALID VALUE
CASE 1: BUSTMG pin = HIGH
Parameter
min
max units
t1
Address Setup to nWR Active
15
nS
t2
t3
Address Hold from nWR Inactive
nCS Setup to WR Active
10
5
nS
nS
nCS Hold from nWR Inactive
0
t4
t5
t6
t7
t8
t9
t10
t11
t12
nS
nS
nS
nS
nS
nS
nS
Cycle Time (nWR
to Next
)**
4TARB*
30***
10
20
20
Valid Data Setup to nWR High
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD
to nWR Low
20
40****
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
nS
nS
0*****
*
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
**** t11 is measured from the latest active (valid) timing among nCS, A0-A2.
*****
t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
**
Note 2:
Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Write cycle for Address Pointer Low Register occurring after a read from Data
Note 3:
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
SMSC COM20022I
Page 67
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
