10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
VALID
A0-A2
t1
t2
t4
nCS
t3
t5
Note 3
nRD
t10
t8
t9
Note 2
t7
t6
nWR
D0-D15
VALID DATA
t11
t12
nIOCS16
VALID VALUE
CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0
min
Parameter
max
units
15
10
5**
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup to nRD Active
t1
t2
t3
t4
t5
t6
t7
t8
t9
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
nRD Low Width
0
4TARB*
40**
20
0
60
20
20
nRD High Width
t10
t11
t12
nWR
to nRD Low
nIOCS16 Output Delay from nCS Low
nIOCS16 Hold Delay from nCS High
40***
0****
*
TARB is the Arbitration Clock Period
T
T
ARB is identical to Topr if SLOW ARB = 0
ARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
nCS may become active after control becomes active, but the access time (t6)
**
will now be 45nS measured from the leading edge of nCS.
***
t11 is measured from the latest active (valid) timing among nCS, A0-A2.
****
t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.
The Microcontroller typically accesses the COM20022 on every other cycle.
Note 1:
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 2:
Note 3:
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
SMSC COM20022I
Page 63
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
