10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
AD0-AD2,
VALID
VALID DATA
D3-D15
t1
t2,
t4
nCS
t3
t12
t11
ALE
nDS
t7
t5
t6
Note 2
t8**
t13
t8
t14
DIR
t16
t9
t10
t15
Previous Value
Invalid
Valid Value
nIOCS16
MUST BE: BUSTMG pin = HIGH
Parameter
min
max
units
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
20
10
10
10
15
30
10
Valid Data Setup to nDS High
Data Hold from nDS High
Cycle Time (nDS
to Next
)**
4TARB*
10
DIR Setup to nDS Active
DIR Hold from nDS Inactive
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
nIOCS16 Hold Delay from ALE Low
nIOCS16 Output Delay from ALE Low
10
20
20
20
20
0
40
*
TARB is the Arbitration Clock Period
ARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
T
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 1:
**
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nDS to the leading edge of the
next nDS.
Note 2:
Write cycle for Address Pointer Low Register occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle
SMSC COM20022I
Page 61
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
