10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
AD0-AD2,
D3-D15
VALID DATA
VALID
t1
t2,
t4
nCS
t3
t10
ALE
nRD
t9
t6
t7
t5
t8
t11
nWR
t13 Note 3
t14
t12
t15
Note 2
nIOCS16
Previous Value
Invalid
Valid Value
MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0
Parameter
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
min
max
units
t1
t2
t3
t4
t5
t6
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
20
10
10
10
15
40
20
nRD Low to Valid Data
0
4TARB*
20
20
60
20
20
0
t7 nRD High to Data High Impedance
t8
t9
Cycle Time (nRD Low to Next Time Low)
ALE High Width
ALE Low Width
nRD Low Width
nRD High Width
t10
t11
t12
t13
t14
t15
nWR
to nRD Low
nIOCS16 Hold Delay from ALE Low
nIOCS16 Output Delay from ALE Low
40
*
T
ARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
ARB is twice Topr if SLOW ARB = 1
opr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
T
T
Note 1:
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 2:
Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Note 3:
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.2 - Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
Revision 09-27-07
Page 60
SMSC COM20022I
DATASHEET
SMSC [ SMSC CORPORATION ]
