Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 7.40 Edge Select 6A
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F61
VCC1
0x00
DEFAULT
BIT
D7:6
D5:4
D3:2
D1:0
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R/W
R/W
R/W
R/W
SE23 Select
SE22 Select
SE21 Select
SE20 Select
USER’S NOTE: Edge-generated interrupts may occur from a change in the edge select bits.
Refer to Table 7.36, "Edge Selection".
Table 7.41 Edge Select 6B
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F62
VCC1
0x00
DEFAULT
BIT
D7:6
D5:4
D3:2
D1:0
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R/W
R/W
R/W
R/W
SE27 Select
SE26 Select
SE25 Select
SE24 Select
USER’S NOTE: Edge-generated interrupts may occur from a change in the edge select bits.
Refer to Table 7.36, "Edge Selection".
7.9.10 Power Fail IRQ
The PWRGD_INT register (Table 7.42) contains the Power Good Interrupt (PGI) bit, D0. When PGI =
‘1’, the (VCC2) PWRGD input has been deasserted; otherwise, PGI = ‘0’.
Note: PGI is not asserted when PWRGD is asserted.
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA8S1HEET
SMSC [ SMSC CORPORATION ]
