Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 7.43 8051_SIRQ Register
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F52
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
8051_IRQ SELECT
8051_IRQ 8051_IRQ Reserved
ENABLE
BIT NAME
8051_IRQ SELECT
Four bits that selects which IRQ is utilized when an interrupt occurs. See Table 7.44.
8051_IRQ ENABLE
This bit must be set to one in order for an interrupt to occur.
8051 IRQ
This bit must set to one in order for the 8051 to assert the mapped interrupt request corresponding to
the 8051_IRQ SELECT bits. The default state for a disabled IRQ is asserted.
Table 7.44 8051 IRQ Mapping Control Bits
8051_IRQ ENABLE
8051_IRQ SELECT
DESCRIPTION
0
1
XXXX
0000
0001
0010
DISABLED
NO INTERRUPT
MAP TO IRQ1
MAP TO IRQ2
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA8S3HEET
SMSC [ SMSC CORPORATION ]
