Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 7.44 8051 IRQ Mapping Control Bits (continued)
8051_IRQ ENABLE 8051_IRQ SELECT
DESCRIPTION
1
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MAP TO IRQ3
MAP TO IRQ4
MAP TO IRQ5
MAP TO IRQ6
MAP TO IRQ7
MAP TO IRQ8
MAP TO IRQ9
MAP TO IRQ10
MAP TO IRQ11
MAP TO IRQ12
MAP TO IRQ13
MAP TO IRQ14
MAP TO IRQ15
7.10
8051 Code Debugging Features
The LPC47N350 8051 code debugging facilities include an external Flash interface, the 8051-controlled
UART. Other capabilities include the 8051 single-step capabilities.
7.10.1 External Flash Interface
The LPC47N350 External Flash Interface enables the read-only portion of the internal 8051 program
memory bus to access an external ROM device using the KBD Scan interface pins. For a detailed
description of the External Flash Interface see Section 7.10.1, "External Flash Interface".
7.10.2 8051 Serial Port
The 8051 serial port can be used during program code development for diagnostic functions. The 8051
serial port pins 8051TX and 8051RX are available on VCC1.
7.10.3 8051 Single-Step Operation
The LPC47N350 8051 interrupt structure provides a method to perform single-step program execution.
When exiting an ISR with an RETI instruction, the 8051 will always execute at least one instruction of
the task program. Therefore, once an ISR is entered, it cannot be re-entered until at least one program
instruction is executed.
To perform a single-step operation, program one of the external interrupts (for example, int_0) to be level
sensitive and write an ISR for that interrupt that terminates as shown in Figure 7.7. The CPU enters
the ISR when int0_n goes low, then waits for a pulse on int0_n. Each time int0_n is pulsed, the CPU
exits the ISR, executes one program instruction, then re-enters the ISR.
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA8S4HEET
SMSC [ SMSC CORPORATION ]
