Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
The PGI bit is the source for the high-performance 8051 Power Fail Interrupt (pfi) input (Figure 7.4). The
VCC2 power fail detect function is implemented as described in Section 7.6, "8051 Ring Oscillator Fail-
Safe Controls," on page 46.
The PGI bit is readable and is cleared by writing a ‘1’ to D0 in the PWRGD_INT register.
Table 7.42 Power Good Interrupt Register (PWRGD_INT)
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F84
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R
R
R
R/WC
PGI
Reserved
7.9.11 8051 External Serial IRQ Generation
The 8051 can assert an interrupt on the serial IRQ stream to support software-generated SCI, SMI, or
PME events (Figure 7.6). The 8051 External Serial IRQ interface is controlled by the 8051_SIRQ register
(Table 7.43).
Note: The 8051 External Serial IRQ is generated and cleared by software.
Serial
8051_IRQ SELECT
IRQ
IRQ Mapping
8051_IRQ
logic
Figure 7.6 8051 External Serial IRQ Block Diagram
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA8S2HEET
SMSC [ SMSC CORPORATION ]
