Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
The RESET_OUT Override function allows the 8051 to take the rest of the LPC47N350 chip (SIO) out
of reset without giving up control (i.e., without stopping its clock).
Note 7.21 In the LPC47N350, iRESET Override mode is the typical mode of operation. When the
iRESET_OVRD bit is asserted, the 8051 clock cannot be stopped. Providing the mode to
stop the 8051 clock is a legacy mode. To stop the 8051 clock, the iRESET_OVRD bit must
be deasserted.
32 KHZ OUTPUT
The 32 kHz Output bit controls the LPC47N350 32 kHz_OUT. When 32kHz Output is ‘0’, the 32kHz
Output Clock is disabled and the 32 kHz_OUT pin is driven low. When 32 kHz Output is ‘1’, the 32 kHz
Output Clock is enabled. The 32kHz Output bit is R/W and disabled by default following Vcc1 POR.
7.8.3.6
8051 LPC Bus Monitor
The 8051 can monitor the state of the LPCPD# input pin using the LPCPD STATUS bit D0 in the LPC
Bus Monitor register (Table 7.3). The LPCPD STATUS bit is the inverse of the LPCPD# pin (see Section
3.1.12, "LPC Power Management" for a description of the LPCPD# pin function).
When the LPCPD STATUS bit is ‘0’, the LPCPD# input pin is deasserted ‘1’. When the LPCPD STATUS
bit is ‘1’, the LPCPD# input pin is asserted ‘0’.
Table 7.13 LPC Bus Monitor Register
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F8A
VCC1
‘0000000X’b
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 TYPE
R
R
R
R
R
R
R
R
RESERVED
LPCPD
BIT NAME
STATUS
Note 7.22 There is no LPCPD STATUS bit default.
7.8.4
LED Controls
The LPC47N350 has three independent LED outputs that are programmable under 8051 control.
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA6S3HEET
SMSC [ SMSC CORPORATION ]
