Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
If SLEEPFLAG=“0”, when PCON bit-0 is set, the 8051 enters “IDLE” mode, whereas if SLEEPFLAG=“1”,
when PCON bit 0 is set the 8051enters “SLEEP” mode. This bit is cleared by the occurrence of any
wake-up events and on VCC1 POR.
7.8.3.5
Output Enable Register
Table 7.12 Output Enable Register
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F3E
VCC1
00000X10b on
VCC1 POR
DEFAULT
00000X1Xb on
VCC2 POR
BIT
D7 - D4
D3
D2
D1
D0
-
-
-
-
-
HOST TYPE
8051 TYPE
R
R/W
R
R/W
R/W
Reserved
iRESET_
OVRD
POWER_
GOOD
iRESET_OUT
32kHz Output
BIT DESCRIPTION
Note 7.20 Output Enable Register VCC1 POR = 0x00000X10, VCC2 POR = 00000X1Xb where X
means the bit holds its setting preceding VCC2 POR.
iRESET_OUT
When POWER_GOOD = 1, iRESET_OUT is controlled by the 8051. When POWER_GOOD = 0,
iRESET_OUT is forced high (within 100nsec) and latched. The nRESET_OUT pin is not driven until
VCC2 is applied. iRESET_OUT cannot be cleared by the 8051 until POWER_GOOD =1.
See Note 7.21 below.
In the LPC47N350, nRESET_OUT is driven high by this sequence of events.
1. Sets STP_CNT to a non-zero value
2. Clears iRESET_OUT bit, causing 8051 STP_CLK bit 0 (see Table 17.6 on page 197) to get set and
STOP Counter to start decrementing
3. When STP_CNT reaches 0, the nRESET_OUT pin deasserts (goes high) at which point the 8051’s
clock stops.
POWER_GOOD
The Power_Good bit D2 reflects the state of the LPC47N350 Vcc2 Power Good pin PWRGD. The
Power_Good bit is read only.
iRESET_OVRD
iRESET Override. When cleared, the iRESET_OUT bit functions as described above. When set,
iRESET_OUT is given direct control over the internal reset and nRESET_OUT pins without requiring
the STOP_CLK counter or affecting the 8051 STP_CLK bit. In the override mode, setting iRESET_OUT
drives nRESET_OUT low and clearing iRESET_OUT drives nRESET_OUT high.
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA6S2HEET
SMSC [ SMSC CORPORATION ]
