Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
7.8.3
8051 Configuration/Control Memory Mapped Registers
7.8.3.1
Disable Register
Table 7.8 Disable Register
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F3F
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
R
R/W
R
R
R/W
R/W
R
R
Reserved Serial
Port
Reserved Reserved UD
System
Flash
Reserved Reserved
BIT NAME
SERIAL PORT - When this bit is asserted ‘1’, the Serial port is enabled. When this bit is deasserted ‘0’,
the Serial port is disabled.
UD - The UD bit is User-Defined. UD bits are maintained by 8051 software, only.
SYSTEM FLASH - When the SYSTEM FLASH bit is asserted ‘1’, the LPC Host Flash programming
interface is disabled. When the SYSTEM FLASH bit is deasserted ‘0’, the LPC Host Flash programming
interface is enabled (see Section 9.5, "LPC Bus Flash Program Access," on page 110).
RESERVED - Logic ‘0’ read only access.
7.8.3.2
Device Rev Register
By reading this register, 8051 firmware can confirm the device revision that it is running on.
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA5S9HEET
SMSC [ SMSC CORPORATION ]
