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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号47N350的Datasheet PDF文件第58页浏览型号47N350的Datasheet PDF文件第59页浏览型号47N350的Datasheet PDF文件第60页浏览型号47N350的Datasheet PDF文件第61页浏览型号47N350的Datasheet PDF文件第63页浏览型号47N350的Datasheet PDF文件第64页浏览型号47N350的Datasheet PDF文件第65页浏览型号47N350的Datasheet PDF文件第66页  
Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
System is running  
(Vcc2 and Vcc1 are on)  
8051 is executing  
Host resets the  
8051STP_CLK[0] bit  
Stop Clock  
Counter  
= 0  
No  
Keyboard firmware  
Yes  
Reset Event is conveyed  
to the 8051 via a command  
from host or GPIO  
nRESET_OUT deasserted  
No  
8051 IRQ  
Yes  
nRESET_OUT deasserted  
and 8051 STP_CLK[0] = 1  
stops the 8051 clock.  
iRESET_OUT register  
bit is reset causing  
nRESET_OUT pin to be  
asserted (See note 1)  
Host may program the  
Flash memory via the  
LPCBUS Flash Program  
Access Mode  
8051 wakes up from Idle  
Mode and starts executing  
from where it left off  
8051 goes into Idle Mode  
Note 1:  
Note 2: In order to leave Idle Mode, the 8051  
must receive an interrupt; typically a software  
timer interrupt will be used.  
Clearing the iRESET_OUT bit causes the following:  
.
8051 STP_CLK[0] = 1  
Stop Clock Counter starts decrementing  
.
Figure 7.2 Typical System Reset Sequence  
7.4  
CPU RESET Sequence  
Often the Host CPU (Pentium) is reset by the hardware signal, CPU_RESET, which is issued by  
software to switch the Processor from Protected, or “Virtual 86”, mode back to Real mode.  
CPU_RESET can be generated from the LPC47N350 8051 core or it may be generated from other logic  
on the PC motherboard. CPU_RESET is meant only to reset the CPU; the rest of the system continues  
to run normally, including the keyboard BIOS in the 8051.  
7.5  
8051 Clock Controls  
The LPC47N350 has two clock source:  
The 8051 may program itself to run off of an internal ring oscillator having a frequency range between  
4 and 12MHz. This is not a precise clock, but is meant to provide the 8051 with a clock source when  
VCC2 is shut down in the system.  
When VCC2 is powered, the 8051 may be programmed to run off the PLL. The 14.318MHz external  
clock source. The 8051 PLL clock frequenies are programmable.  
7.5.1  
Frequency Controls  
The KBDCLK ENABLE bit controls the running of the 8051 PLL clock and the KBDCLK[1:0] control bits  
in the KSTP_CLK register (MMCR 0x7F27) select the 8051 system clock frequencies. The LPC47N350  
8051 can run up to 32MHz.  
Revision 1.1 (01-14-03)  
SMSC LPC47N350  
DATA4S4HEET  
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