Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
6. After a maximum total elapsed time of less than 6 µs after PWRGD pin changes from “1” to “0”, the
8051 system clock is switched to the ring oscillator.
Note: Following a power fail event, VCC2 must be ≥ 3V and the 14.318MHz input clock CLOCKI must
remain stable for 10µs min. (Figure 2.2).
An 8051power-fail interrupt (pfi) is generated to inform the 8051 of the power fail event.
There are four functional power-fail event scenarios. The actions taken for each are described in
Table 7.5.
Table 7.5 Power-Fail Event Actions
ACTIONS
ASSERT
ASSERT
PGI (SEE
Note 7.2)
ASSERT RING
OSC. (SEE
Note 7.3)
8051
FLASH
ACCESS
8051 STATE
DESCRIPTION
1
2
3
4
Sleeping on
Ring Osc.
yes
-
-
No fail-safe actions taken
Running on
Ring Osc.
-
-
No fail-safe actions taken; 8051 can
respond to PFI if needed.
Running on
PLL
yes
-
Internal PWRGD is delayed until ring osc.
is asserted.
Stopped on
PLL
yes
Internal PWRGD is delayed until ring osc.
is asserted and the 8051 controls the
flash.
Note 7.2 PGI is the Powergood Interrupt bit D0 in the PWRGD_INT register (see Section 7.9.10,
"Power Fail IRQ," on page 81).
Note 7.3 The 8051 is switched to the Ring Oscillator after a delay. (See PWRGD and VCC1_PWRGD
timing is illustrated in Figure 2.1 through Figure 2.3).
7.7
8051 Memory Map
The LPC47N350 8051 has two types of Flash support:
64k embedded Flash ROM (see Chapter 8, 64K Embedded Flash ROM).
or
The External Flash Interface using the KBD Scan Interface that enables the 8051 program memory to
reside in an external ROM device (see Section 9.10.10, "Flash Data Register," on page 125).
The 64k embedded Flash ROM flash support provides a 512-byte Scratch ROM from which the 8051
can execute program code when the 8051 Code Fetch Access interface or when the 8051 Program
Access interface is selected by the Flash Program Interface Decoder (see Section 9.2, "Flash Program
Interface Decoder"). The MMC bit in CONFIGURATION REGISTER 0 (MMCR 0x7FF4 see
Section 7.8.3.4) controls the Scratch ROM.
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA4S7HEET
SMSC [ SMSC CORPORATION ]
