Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Chapter 7 8051 Embedded Controller
7.1
8051 Functional Overview
The High-Performance 8051 embedded controller is a fully static CMOS core compatible with the
industry-standard 80C51 microcontroller. The high-performance 8051 features include:
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2.5X average instruction execution speed improvement over the entire instruction set; i.e., typical 4-
clock instruction cycle in high-performance 8051 vs. 12-clock instruction cycle in standard 8051.
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Faster clock speed: 32MHz or higher vs. 16MHz in standard 8051.
Dual Data Pointers
More Interrupts: Power-Fail, External Interrupt 2, External Interrupt 3, etc.
A set of External Memory/Mapped Control Registers provides the 80C51 core with the ability to
directly control many functional blocks of the LPC47N350.
7.1.1
Features
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Internal 64K Flash ROM
Programmed From Direct Parallel Interface, 8051, or LPC Host
2k-Byte Lockable Boot Block
512 Byte Scratch ROM
256 Bytes Internal Data RAM
512 Bytes of External Data RAM
256 Byte External Memory-Mapped Control Register Area
128 Byte Special Function Register Area
Access to 256 Byte RTC CMOS RAM
8042 style Keyboard Controller Host Interface
Eleven Interrupt Sources
Watch Dog Timer (WDT)
Ring Oscillator with Fail Safe Control
7.2
High-Performance 8051 Implemented Features
There are five significant features implemented in the high-performance 8051 core. These features,
summarized in Table 7.1, are described more fully in the sub-sections that follow.
Table 7.1 High-Performance 8051 Implemented Features
FEATURE
VALUE
DESCRIPTION
Internal RAM Size
256
The internal RAM size is 256 bytes to maintain compatibility with
existing implementations.
(bytes)
Internal Timers
3
There are three internal Timers (T0, T1 & T2).
The external inputs for Timer/Counter T0, T1, and T2, as well as
the Timer/Counter 2 capture/reload trigger T2EX are not
supported in the LPC47N350.
Serial Ports
1
There is one Serial Port.
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA4S1HEET