Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU
nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout
interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it.
These FIFO related features allow optimization of CPU/UART transactions and are especially useful
given the higher baud rate capability (256 kbaud).
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA3S8HEET