Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 5.6 UART Baud Rates
HIGH SPEED
BIT
DESIRED
DIVISOR USED TO
PERCENT ERROR DIFFERENCE BETWEEN
BAUD RATE
GENERATE 16X CLOCK
DESIRED AND ACTUAL (SEE Note 5.2)
(SEE Note 5.3)
50
75
2304
1536
1047
857
768
384
192
96
0.1
X
-
110
-
134.5
150
0.4
-
300
-
600
-
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
-
64
-
58
0.5
48
-
32
-
24
-
16
-
12
-
6
-
-
3
2
0.16
1
32770
32769
1
Note 5.2 The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Note 5.3 The High Speed bit is located in the Device Configuration Space.
Baud Rates
Using 1.8462 MHz Clock for Baud Rate <= 57.6K;
Using 1.8432 MHz Clock for Baud Rate = 115.2k;
Using 3.6864 MHz Clock for Baud Rate = 230.4k;
Using 7.3728 MHz Clock for Baud Rate = 460.8k
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATA3S3HEET
SMSC [ SMSC CORPORATION ]
