Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Divisor Latch Access Bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the
Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the
Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.
5.1.7
Modem Control Register (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
This register is used to enable the UART interrupt and enable the loopback feature. The contents of the
MODEM control register are described below.
BIT 0
This bit controls the Data Terminal Ready (nDTR) output. This bit is not supported.
BIT 1
This bit controls the Request To Send (nRTS) output. This bit is not supported.
BIT 2
This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read
or written by the CPU.
BIT 3
Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial
port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial
port interrupt outputs are enabled.
BIT 4
This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic
"1", the following occur:
1. The TXD is set to the Marking State (logic "1").
2. The receiver Serial Input (RXD) is disconnected.
3. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input.
4. Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the
diagnostic mode, the receiver and the transmitter interrupts are fully operational. The interrupts are still
controlled by the Interrupt Enable Register.
BITS 5 - 7
These bits are permanently set to logic zero.
5.1.8
Line Status Register (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
BIT 0
Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received
and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading
all of the data in the Receive Buffer Register or the FIFO.
BIT 1
Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the
next character was transferred into the register, thereby destroying the previous character. In FIFO
mode, an overrun error will occur only when the FIFO is full and the next character has been completely
Revision 1.1 (01-14-03)
SMSC LPC47N350
DATA3S0HEET
SMSC [ SMSC CORPORATION ]
