Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table B.11 T2CON Register Bit Descriptions
FUNCTION
BIT
T2CON.7
TF2 Timer 2 overflow flag. Hardware will set TF2 when the Timer 2 overflows from
FFFFh. TF2 must be cleared to 0 by the software. TF2 will only be set to a 1 if
RCLK and TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt
if enabled.
T2CON.6
T2CON.5
Reserved. This bit should be written as ‘0’.
RCLK Receive clock flag. Determines whether Timer 1 or Timer 2 is used for Serial
Port 0 timing of received data in serial mode 1 or 3. RCLK =1 selects Timer 2
overflow as the receive clock. RCLK =0 selects Timer 1 overflow as the receive
clock.
T2CON.4
TCLK Transmit clock flag. Determines whether Timer 1 or Timer 2 is used for Serial
Port 0 timing of transmit data in serial mode 1 or 3. RCLK =1 selects Timer 2
overflow as the transmit clock. RCLK =0 selects Timer 1 overflow as the transmit
clock.
T2CON.3
T2CON.2
T2CON.1-0
Reserved. This bit should be written as ‘0’.
TR2. Timer 2 run control flag. TR2 = 1 starts Timer 2. TR2 = 0 stops Timer 2.
Reserved. This bit should be written as ‘0’.
B.3.8
RCAP2L
The RCAP2L register is the 16-bit LSB reload value (RV[7:0]) when Timer 2 is configured for auto-reload
mode.
Table B.12 RCAP2L Register - SFR CAH
CAh
SFR ADDRESS
POWER
VCC1
0x00
DEFAULT
BIT
D7
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
R/W
RV7
TYPE
RV6
RV5
RV4
RV3
RV2
RV1
RV0
BIT NAME
B.3.9
RCAP2H
The RCAP2H register is the 16-bit MSB reload value (RV[15:8]) when Timer 2 is configured for auto-
reload mode.
Revision 1.1 (01-14-03)
322
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
