Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table B.20 EIE Register - SFR E8H
E8h
SFR ADDRESS
POWER
VCC1
0xE0
DEFAULT
BIT
D7
D6
D5
D4
D3
R/W
D2
R/W
D1
R/W
D0
R/W
R
R
R
R
TYPE
Reserved
EX5
EX4
EX3
EX2
BIT NAME
Table B.21 EIE Register Bit Descriptions
FUNCTION
BIT
EIE.7-5
EIE.4
Reserved. Read as ‘1’.
Reserved. Read and Write as ‘0’.
EIE.3
EX5 Enable external interrupt 5. EX5 = 0 disables external interrupt 5 (int5_n).
EX5 = 1 enables interrupts generated by the int5_n pin.
EIE.2
EIE.1
EIE.0
EX4 Enable external interrupt 4. EX4 = 0 disables external interrupt 4 (int4). EX4
= 1 enables interrupts generated by the int4 pin.
EX3 Enable external interrupt 3. EX3 = 0 disables external interrupt 3 (int3_n).
EX3 = 1 enables interrupts generated by the int3_n pin.
EX2 Enable external interrupt 2. EX2 = 0 disables external interrupt 2 (int2). EX2
= 1 enables interrupts generated by the int2 pin.
B.3.15 EIP
The EIP register contains the external interrupt priority controls for the extended interrupt unit.
Table B.22 EIP Register - SFR F8H
F8h
SFR ADDRESS
POWER
VCC1
0xE0
DEFAULT
BIT
D7
D6
D5
D4
D3
R/W
D2
R/W
D1
R/W
D0
R/W
R
R
R
R
TYPE
Reserved
PX5
PX4
PX3
PX2
BIT NAME
Revision 1.1 (01-14-03)
326
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
