Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 2.2 Pin Function Description (continued)
POWER
BUFFER MODES
NOTES
NAME
DESCRIPTION
PLANE
(SEE Note 2.1)
Note 2.15
SGPIO31/
SPDOUT
8051 SFR bit-wise addressable GPIO Serial
Peripheral Data Output. SPDOUT can be
configurated as bi-directional Data In/Data Out
VCC1
IO8/IO8
SGPIO32/
SPDIN
8051 SFR bit-wise addressable GPIO Serial
Peripheral Data Input
VCC1
IO8/I
SGPIO33
8051 SFR bit-wise addressable GPIO
LPC/8051 addressable GPIO
VCC1
VCC1
IO8
IO8
LGPIO50 -
LGPIO53
Note 2.3
LGPIO60 -
LGPIO63
LPC/8051 addressable GPIO
VCC1
(IO8/OD8)
MISCELLANEOUS (15)
32kHz_OUT
CLK_OUT
32.768kHz Output Clock
VCC1
VCC2
O8
Programmable clock output.
Off (default)
1.8432 MHz
14.318 MHz
16 MHz
O16
24 MHz
48 MHz
CLOCKI
MODE
14.318MHz Clock Input
VCC2
VCC1
VCC1
ICLK
Note 2.11
Note 2.7
Configuration Ports Base Address Select
I
TEST_PIN
No Connect. This pin provides acess to the
SMSC board level XNOR-Chain test.
See Chapter 26, "XNOR Chain Test Mode," on
page 275.
-
VCC1_PWR
GD
VCC1 Power Good Input
VCC1
VCC2
I
nRESET_O
UT
System Reset
O16
nBAT_LED
Battery LED (0 = ON)
VCC1
VCC1
OD12
nPWR_LED/
8051TX
Power LED (0 = ON)
8051 TX Input
OD12/OD12
nFDD_LED/
8051RX
Floppy LED (0 = ON)
8051 RX Input
VCC1
OD12/I
nDMS_LED
PWRGD
PGM
Dead Man Switch LED (0 = ON)
VCC2 Power Good Input
VCC1
VCC1
VCC1
OD12
I
Note 2.7
Note 2.9
Flash Programming Enable
IPD
(see Section 9.6, "ATE Flash Program Access")
nFWP
nEA
Flash Boot Block Write Protect (see Section
8.5, "8051 Flash Boot Block Protect Controls")
VCC1
VCC1
I
I
Internal/External Flash Select (see Section 9.7,
"External Flash Interface")
SMSC LPC47N350
7
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
