Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
When the PWM2 Clock Multiplier bit = “0”, no clock multiplier is used. When the PWM2 Clock Multiplier
bit = “1”, the clock speed determined by the PWM2 Clock Select [1:0] bits is doubled (Table 18.2)
PWM2 Clock Select 1, D6
The PWM2 Clock Select 1 bit, D6 is used with the PWM2 Clock Multiplier bit, D7, the PWM2 Clock
Select 0 bit, MBX95.7, and the Frequency Multiplier bits, MBXB2.0 and MBXB2.1, to determine the
PWM2 F
OUT .
The affects of the Fan Clock Select [1:0] bits are shown in Table 18.2.
PWM1 STDBY Clock, D5
The PWM1 STDBY CLOCK bit D5 is used to determine the PWM1 controller clock source.
When the PWM1 STDBY CLOCK bit = “1”, the PWM1 controller clock source is the 32.768kHz RTC
clock (VCC1/VCC2). The available PWM1 F
frequencies when D5 = “1” are shown in Table 18.1.
OUT
When the PWM1 STDBY CLOCK bit = “0”, the PWM1 controller clock source is the system clock
(VCC2). The available PWM1 F frequencies when D5 = “0” are shown in Table 18.1.
OUT
The PWM1 STDBY CLOCK bit default = “1”.
PWM0 STDBY Clock, D4
The PWM0 STDBY CLOCK bit, D4 is used to determine the PWM0 controller clock source.
When the PWM0 STDBY CLOCK bit = “1”, the PWM0 controller clock source is the 32.768kHz RTC
clock (VCC1/VCC2). The available PWM0 F
frequencies when D4 = “1” are shown in Table 18.1.
OUT
When the PWM0 STDBY CLOCK bit = “0”, the PWM0 controller clock source is the system clock
(VCC2). The available PWM0 F frequencies when D4 = “0” are shown in Table 18.1.
OUT
The PWM0 STDBY CLOCK bit default = “1”.
PWM1 Clock Multiplier, D3
The PWM1 Clock Multiplier bit, D3 is used with the PWM1 Clock Select 1 bit, D1, the PWM1 Clock
Select 0 bit, MBX93.7, and the Frequency Multiplier bits, MBXB1.0 and MBXB1.1, to determine the
PWM1 F
when the PWM1 STDBY CLOCK select bit is “0”.
OUT
When the PWM1 Clock Multiplier bit = “0”, no clock multiplier is used. When the PWM1 Clock Multiplier
bit = “1”, the clock speed determined by the PWM1 Clock Select [1:0] bits is doubled (Table 18.1).
The PWM1 Clock Multiplier bit does not affect the PWM1 F
bit is “1”.
when the PWM1 STDBY CLOCK select
OUT
PWM0 Clock Multiplier, D2
The PWM0 Clock Multiplier bit, D2 is used with the PWM0 Clock Select 1 bit, D0, the PWM0 Clock
Select 0 bit, MBX92.7, and the Frequency Multiplier bits, MBXB1.0 and MBXB1.1, to determine the
PWM0 F
when the PWM0 STDBY CLOCK select bit is “0”.
OUT
When the PWM0 Clock Multiplier bit = “0”, no clock multiplier is used. When the PWM0 Clock Multiplier
bit = “1”, the clock speed determined by the PWM0 Clock Select [1:0] bits is doubled (Table 18.1).
The PWM0 Clock Multiplier bit does not affect the PWM0 F
bit is “1”.
when the PWM0 STDBY CLOCK select
OUT
PWM1 Clock Select 1, D1
The PWM1 Clock Select 1 bit, D1 is used with the PWM1 Clock Multiplier bit, D3, the PWM1 Clock
Select 0 bit, MBX93.7, and the Frequency Multiplier bits, MBXB2.0 and MBXB2.1, to determine the
PWM1 F
.
OUT
The affects of the PWM1 Clock Select [1:0] bits are shown in Table 18.1.
SMSC LPC47N350
205
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
