Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Duty Cycle Control, D6 – D1
The Duty Cycle Control (DCC) bits determine the PWM fan duty cycle. The LPC47N350 has ≈1.56%
duty cycle resolution.
When DCC = “000000” (min. value), F
is always low. When DCC is “111111” (max. value), F
OUT
th
OUT
th
is almost always high; i.e., high for 63/64 and low for 1/64 of the F
period.
OUT
Generally, the F
duty cycle (%) is (DCC ÷ 64) × 100.
OUT
PWM Clock Control, D0
The PWM Clock Control bit, D0 is used to override the Duty Cycle Control bits and force F
high.
always
OUT
When D0 = “0”, the DCC bits determine the F
regardless of the state of the DCC bits.
duty cycle. When D0 = 1, F
is always high,
OUT
OUT
18.3
PWM Control Register
The PWM Control register contains PWM Clock Select 1 and PWM Clock Multiplier for each of the three
PWM Speed Controllers, PWM0, PWM1, and PWM2. The Standby Clock control bit is implemented only
on PWM0 and PWM1.
The PWM Control register is MBX9D register (See Table 18.7). The default value for the PWM Control
Register is 0x30. The default value takes effect on VCC1 POR.
For PWM3 Control Register, see Table 18.8.
Table 18.7 PWM Control Register
0x9D
MAILBOX INDEX
8051 ADDRESS
POWER
0x7F28
VCC1
0x30
DEFAULT
BIT
D7
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
R/W
MBX TYPE
8051 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM2
CLOCK
MULTI-
PLIER
PWM2
PWM1
PWM0
STDBY
CLOCK
PWM1
CLOCK
MULTI-
PLIER
PWM0
CLOCK
MULTI-
PLIER
PWM1
PWM0
CLOCK
STDBY
CLOCK
CLOCK
BIT NAME
SELECT CLOCK
1
SELECT SELECT
1
1
PROGRAMMER’S NOTE: The PWMx STDBY CLOCK bits, D4 and D5, should not be switched when PWRGD is
inactive; i.e., when VCC2 = 0V.
PWM2 Clock Multiplier, D7
The PWM2 Clock Multiplier bit, D7 is used with the PWM2 Clock Select 1 bit, D6, the PWM2 Clock
Select 0 bit, MBX95.7, and the Frequency Multiplier bits, MBXB2.0 and MBXB2.1, to determine the
PWM2 F
OUT .
Revision 1.1 (01-14-03)
204
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
