Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Note: There are four PS/2 Control Registers, one for each channel.
PS2_T/R
PS/2 Channel Transmit/Receive (default = 0). This bit is only valid when PS2_EN=1 and sets the PS2
logic for automatic transmission or reception when PS2_T/R equals ‘1’ or ‘0’ respectively.
When set, the PS/2 channel is enabled to transmit data. To properly initiate a transmit operation, this
bit must be set prior to writing to the Transmit Register; writes are blocked to the Transmit Register
when this bit is not set. Upon setting the PS2_T/R bit, the channel will drive its CLK line low and then
float the DATA line and hold this state until a write occurs to the Transmit Register or until the PS2_T/R
bit is cleared. Writing to the Transmit Register initiates the transmit operation. LPC47N350 drives the
data line low and, within 80ns, floats the clock line (externally pulled high by the pull-up resistor) to signal
to the external PS/2 device that data is now available. The PS2_T/R bit is cleared on the 11th clock
edge of the transmission or if a Transmit Timeout error condition occurs.
Note: If the PS2_T/R bit is set while the channel is actively receiving data prior to the leading edge of
the 10th (parity bit) clock edge, the receive data is discarded. If this bit is not set prior to the
10th clock signal, then the receive data is saved in the Receive Register.
When the PS2_T/R bit is cleared, the PS/2 channel is enabled to receive data. Upon clearing this bit,
if RDATA_RDY=0, the channel’s CLK and DATA will float waiting for the external PS/2 device to signal
the start of a transmission. If the PS2_T/R bit is set while RDATA_RDY=1, then the channel’s DATA
line will float but its CLK line will be held low, holding off the peripheral, until the Receive Register is
read.
PS2_EN
PS2 Channel ENable (default = 0). When PS2_EN=1, the PS/2 State machine is enabled allowing the
channel to perform automatic reception or transmission depending on the bit value of PS2_T/R. When
PS2_EN = 0, the channel’s automatic PS/2 state machine is disabled and the channel can be bit-banged
through the WR_DATA and WR_CLK bits in the Control Register and the RD_DATA and RD_CLK bits
in the Status Register. Thus, when PS2_En=0, the channel’s CLK and DATA lines are forced to the
level specified in the Control Register WR_CLK and WR_DATA bits.
Note: If the PS2_EN bit is cleared prior to the leading edge (falling edge) of the 10th (parity bit) clock
edge the receive data is discarded (RDATA_RDY remains low). If the PS2_EN bit is cleared
following the leading edge of the 10th clock signal, then the receive data is saved in the Receive
Register (RDATA_RDY goes high) assuming no parity error.
PROGRAMMER’S NOTE: To abort a transfer from the peripheral the WR_CLK and PS2_EN bits can be set low
simultaneously and held for at least 300us.
PARITY
Bits [3:2] of the Control Register are used to set the parity expected by the PS/2 channel state machine.
These bits are therefore only valid when PS2_EN=1.
Bits[3:2] = 00: Receiver expects Odd Parity (default).
= 01: Receiver expects Even Parity.
= 10: Receiver ignores level of the parity bit (10th bit is not interpreted as a parity bit).
= 11: Reserved.
STOP
Bits [5:4] of the Control Register are used to set the level of the stop bit expected by the PS/2 channel
state machine. These bits are therefore only valid when PS2_EN=1.
Bits[5:4] = 00: Receiver expects an active high stop bit.
= 01: Receiver expects an active low stop bit.
Revision 1.1 (01-14-03)
160
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
