Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
and the CLK line is released to hi-z following a read of this register. This automatically holds off further
receive transfers until the 8051 has had a chance to get the data.
Table 14.4 SMSC Receive Registers (A–D)
n/a
HOST
ADDRESS
0x7F41 (CHAN A)
0x7F45 (CHAN B)
0x7F49 (CHAN C)
0x7F4D (CHAN D)
8051 ADDRESS
VCC2
POWER
0xFF
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R
R
R
R
Receive Data
Note 14.12 The Receive Register is initialized to 0xFF after a read or after a Timeout has occurred.
Note 14.13 The channel can be enabled to automatically transmit data (PS2_EN=1) by setting PS2_T/R
while RDATA_RDY is set, however a transmission can not be kicked off until the data has
been read from the Receive Register.
Note 14.14 An interrupt is generated on the low to high transition of RDATA_RDY.
Note 14.15 If a receive timeout (REC_TIMEOUT=1) or a transmit timeout (XMIT_TIMEOUT=1) occurs,
the channel is busied (CLK held low) for 300us (Hold Time) to guarantee that the peripheral
aborts. Writing to the Transmit Register will be allowed, however the data written will not
be transmitted until the Hold Time expires and until the PS/2 status register is read.
Note 14.16 All bits in this register are read only.
Revision 1.1 (01-14-03)
158
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
