Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 14.2 PS/2 Device Data Stream Bit Definitions
Start Bit
8 data bits, least sig bit first
Parity Bit
Stop Bit
Always 0
Odd on xmit
Prog. on rec.
High on xmit
Prog. on rec.
14.3
SMSC PS/2 Memory Mapped Control Registers
Each SMSC PS/2 channel has a separate set of identical control registers: Transmit, Receive, Control,
and Status. These are shown in Table 7.6 between addresses 0x7F41 and 0x7F4F. The transmit and
receive register share the same address (for example, PS/2 Chan A Tx/Rx) In addition, one register is
shared by all four channels to provide RX_Busy indicators.
14.3.1 SMSC PS/2 Transmit Registers
The byte written to this register, when PS2_T/R, PS2_EN, and XMIT_IDLE are set, is transmitted
automatically by the PS/2 channel control logic. If any of these three bits (PS2_T/R, PS2_EN, and
XMIT_IDLE) are not set, then writes to this register are ignored. On successful completion of this
transmission or upon a Transmit Time-out condition, the PS2_T/R bit is automatically cleared and the
XMIT_IDLE bit is automatically set. The PS2_T/R bit must be written to a ‘1’ before initiating another
transmission to the remote device.
Table 14.3 SMSC Transmit Registers (A–D)
n/a
HOST
ADDRESS
0x7F41 (CHAN A)
0x7F45 (CHAN B)
0x7F49 (CHAN C)
0x7F4D (CHAN D)
VCC2
8051 ADDRESS
POWER
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
W
W
W
W
W
W
W
W
Transmit Data
Note 14.9 Even if PS2_T/R, PS2_EN, and XMIT_IDLE are all set, writing the Transmit Register will not
kick off a transmission if RDATA_RDY is set. The automatic PS2 logic forces data to be
read from the Receive Register before allowing a transmission.
Note 14.10 An interrupt is generated on the low to high transition of XMIT_IDLE.
Note 14.11 All bits of this register are write only.
14.3.2 SMSC PS/2 Receive Registers
When PS2_EN=1 and PS2_T/R=0, the PS2 Channel is set to automatically receive data on that channel
(both the CLK and DATA lines will float waiting for the peripheral to initiate a reception by sending a
start bit followed by the data bits). After a successful reception, data is placed in this register and the
RDATA_RDY bit is set and the CLK line is forced low by the PS2 channel logic. RDATA_RDY is cleared
SMSC LPC47N350
157
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
