Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Note 14.4 Once a transmission has begun, the PS/2 `peripheral is allowed up to 300us per bit transfer.
If the time between falling clock edges exceeds 300us a transfer timeout occurs resulting in
either XMIT_TIMEOUT or REC_TIMEOUT being set along with the generation of an
interrupt.
Note 14.5 Once a transmission has started, the PS/2 peripheral has approximately 2ms to complete
the transfer. This transfer timeout applies to transmissions as well as receptions. In the
case of
a
transmission (reception), if
a
2ms timeout occurs the
XMIT_TIMEOUT(REC_TIMEOUT) bit in the status register is set and an interrupt is
generated.
Note 14.6 When the controller is ready to transmit data, it floats the data line and drives the clock line
low. Once data is written to the Transmit Register, the data line is driven low and after a
delay the clock line is released (floated) so that the PS/2 peripheral knows data is ready.
Releasing the clock signals the start of a transmission. The PS/2 peripheral has 25ms to
acknowledge the transmit start condition above by driving the clock line low. If the PS/2
peripheral does not acknowledge in the allotted time, then a Transmit timeout occurs: setting
the XMIT_TIMEOUT error bit in the Status register and generating an interrupt.
Note 14.7 By clearing the PS/2 channels PS2_EN bit in its Control Register, the PS/2 Channel can be
operated in a fully software controlled “Bit-bang” mode. This allows operation of auxiliary
devices that do not meet standard PS/2 protocol timing handled by the LPC47N350’s PS/2
Logic block.
Note 14.8 See Section 29.7, "PS/2 Timing" for timing information.
PROGRAMMER’S NOTE:
1. The PS2_T/R bit should never be used to abort an active transmission by setting it to 0 in the middle
of a transmission. To properly abort, refer to Programmer’s Note
2. To abort a transfer from the peripheral, the WR_CLK and PS2_EN bits can be set low simultaneously
and held for at least 300us.
3. A transmission may be started immediately if PS2_T/R is set to “1” within 30us of a XMIT finished
Interrupt or within 30us of reading the Receive Register, otherwise the channel may be in the middle
of receiving data from the peripheral. If PS2_T/R is not set to one under the above conditions,
software should wait 300us before transmitting to insure that the peripheral has aborted it’s
transmission.
PDAT_A
PCLK_A
PS2_CHAN_A
MEMORY
MAPPED
CONTROL
REGISTERS
PDAT_B
PCLK_B
PDAT_C
PCLK_C
PDAT_D
PCLK_D
PS2_CHAN_B
PS2_CHAN_C
PS2_CHAN_D
8051
Figure 14.1 SMSC PS/2 Logic Block Diagram
14.2
PS/2 Data Frame
Data transmissions to and from the auxiliary device connector on each PS/2 channel consist of an 11-
bit data stream sent serially over the data line. Table 14.2 shows the function of each bit.
Revision 1.1 (01-14-03)
156
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
