Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Chapter 14 PS/2 Device Interface
The LPC47N350 has four independent PS/2 serial ports implemented in hardware which are directly
controlled by the on chip 8051 The hardware implementation eliminates the need to bit bang I/O ports
to generate PS/2 traffic, however bit banging is still available if required.
Each of the four PS/2 serial channels use a synchronous serial protocol to communicate with the
auxiliary device. Each PS/2 channel has two signal lines: Clock and Data. Both signal lines are bi-
directional and employ open drain outputs capable of sinking 16mA. A pull-up resistor (typically 10K)
is connected to the clock and data lines. This allows either the LPC47N350 SMSC PS/2 logic or the
auxiliary device to control both lines. Regardless, the auxiliary device provides the clock for transmit
and receive operations. The serial packet is made up of eleven bits, listed in order as they will appear
on the data line: start bit, eight data bits (least significant bit first), odd parity, and stop bit. Each bit cell
is from 60µS to 100µS long.
The SMSC PS/2 interface is available in the LPC47N350. The SMSC PS/2 registers are shown in
Table 7.7, "8051 On-Chip External Memory Mapped Registers" between addresses 0x7F41 and 0x7F4F.
Table 14.1 Pin Definitions
PIN NAME
SMSC PS/2 FUNCTION
SMSC PS/2 DESCRIPTION
GPIO20
GPIO21
IMCLK
IMDAT
KCLK
PS2CLK
PS2DAT
IMCLK
IMDAT
KCLK
Channel D Serial Clock
Channel D Serial Data
Channel C Serial Clock
Channel C Serial Data
Channel B Serial Clock
Channel B Serial Data
Channel A Serial Clock
Channel A Serial Data
KDAT
KDAT
EMCLK
EMDAT
EMCLK
EMDAT
All PS/2 Serial Channel signals (CLK and DAT) are driven by open collector (TYPE I/OD16) drivers
pulled to VCC2 (+3.3V nominal) through 10K-ohm resistors.
14.1
SMSC PS/2 Logic Overview
The SMSC PS/2 logic allows the host to communicate to any serial auxiliary devices compatible with
the PS/2 interface through any one of four channels. The PS/2 Logic consists of four identical SMSC
PS/2 channels, each containing a set of four operating registers. The four Channels are PS/2 Chan A,
PS/2 Chan B, PS/2 Chan C, and PS/2 Chan D. During a reception, the LPC47N350 latches the data
on the high to low transition of the clock. During a transmission, the LPC47N350 transitions the data
line on the high to low transition of the clock. See Figure 14.1, "SMSC PS/2 Logic Block Diagram".
Note 14.1 Each PS/2 channel has the ability to “busy” the communication link by pulling the clock line
low. This is accomplished by simultaneously clearing the PS2_EN and WR_CLK bits in the
Control Register.
Note 14.2 Each PS/2 channel has the ability to abort, prior to the parity bit (10th bit), the transfer in
progress.
Note 14.3 Clock bit time (cycle time) typically varies between 60 and 100 us. The LPC47N350 PS/2
Logic is designed such that it is immune to variations in the clock cycle times within the limit
of the transfer timeout.
SMSC LPC47N350
155
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
