ST2202A
19. DIRECT MEMORY ACCESS (DMA)
boundaryꢀsmoothly,ꢀbutꢀDMRꢀisꢀonlyꢀvalidꢀforꢀDMS.ꢀThe
DMR can automatic increases when DMS across bank
boundary.
Toꢀspeedꢀupꢀtheꢀmemoryꢀaccessꢀofꢀthisꢀsystem,ꢀaꢀ
sequentialꢀdirectꢀmemoryꢀaccessꢀ(DMA)ꢀcontrollerꢀisꢀ
designedꢁin.ꢀDMAꢀcanꢀperformꢀmemoryꢀtransferꢀfunctionꢀ
moreꢀefficientꢀthanꢀCPUꢀdoes.ꢀWhileꢀDMAꢀworking,ꢀdataꢀ
ROMꢀregisterꢀ(DRR)ꢀwillꢀdisableꢀandꢀDMAꢀuseꢀDMAꢀ
memoryꢀbankꢀregisterꢀ(DMR)ꢀtoꢀaccessꢀROM.ꢀAfterꢀDMAꢀ
complete,ꢀROMꢀbankꢀcontrolꢀstillꢀreturnꢀtoꢀDRR.ꢀ
WithꢀtheꢀhelpꢀofꢀDMRꢀcanꢀmakeꢀDMSꢀacrossꢀbankꢀ
ꢀ
Note:ꢀLocationꢀofꢀsourceꢀdataꢀcanꢀnotꢀfallꢀinꢀtheꢀrangeꢀ
ofꢀinternalꢀSRAM(ꢀthatꢀisꢀtheꢀrangeꢀofꢀ
0100H~FFFH).ꢀ
ꢀ
CPU
SRAM
ROM
LCD_CTL
LCD
DMA
ꢀ
FIGURE 19-1 System Block Diagram
ꢀ
19.1 DMA Control Register
Theꢀcontrolꢀregisterꢀisꢀshownꢀasꢀfollowing:ꢀ
ꢀ
TABLE 19-2 DMA Control Register (LCTL)
Address Name R/W
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
Default
$028 DMSL
$029 DMSH
$02A DMDL
$02B DMDH
$02C DCNTL
$02D DCNTH
Wꢀ DMS[7]ꢀ DMS[6]ꢀ DMS[5]ꢀ DMS[4]ꢀ DMS[3]ꢀ DMS[2]ꢀ DMS[1]ꢀ DMS[0]ꢀ ????ꢀ????ꢀ
Wꢀ DMS[15]ꢀ DMS[14]ꢀ DMS[13]ꢀ DMS[12]ꢀ DMS[11]ꢀ DMS[10]ꢀ DMS[9]ꢀ DMS[8]ꢀ ????ꢀ????ꢀ
Wꢀ DMD[7]ꢀ DMD[6]ꢀ DMD[5]ꢀ DMD[4]ꢀ DMD[3]ꢀ DMD[2]ꢀ DMD[1]ꢀ DMD[0]ꢀ ????ꢀ????ꢀ
Wꢀ DMD[15]ꢀ DMD[14]ꢀ DMD[13]ꢀ DMD[12]ꢀ DMD[11]ꢀ DMD[10]ꢀ DMD[9]ꢀ DMD[8]ꢀ ????ꢀ????ꢀ
Wꢀ DCNT[7]ꢀ DCNT[6]ꢀ DCNT[5]ꢀ DCNT[4]ꢀ DCNT[3]ꢀ DCNT[2]ꢀ DCNT[1]ꢀ DCNT[0]ꢀ ????ꢀ????ꢀ
Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
DMAMꢀ DCNT[11]ꢀ DCNT[10]ꢀ DCNT[9]ꢀ DCNT[8]ꢀ ꢁꢀꢁꢀꢁ?ꢀ????ꢀ
$036 DMRL R/Wꢀ DMR[7]ꢀ DMR[6]ꢀ DMR[5]ꢀ DMR[4]ꢀ DMR[3]ꢀ DMR[2]ꢀ DMR[1]ꢀ DMR[0]ꢀ 0000ꢀ0000ꢀ
$037 DMRH
R/Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
DMR[10]ꢀ DMR[9]ꢀ DMR[8]ꢀ ꢁꢀꢁꢀꢁꢀꢁꢀꢁ000ꢀ
ꢀ
DMS[15:0] :ꢀ ꢀ DMAꢀsourceꢀdataꢀstartingꢀaddressꢀregisterꢀ
ꢀ
DMD[15:0]:ꢀ ꢀ DMAꢀdestinationꢀdataꢀstartingꢀaddressꢀregisterꢀ
ꢀ
DCNT[11:0]:ꢀ DMAꢀmovingꢀdataꢀbyteꢀcounterꢀregisterꢀ
ꢀ
DMR[10:0]:
ꢀ
DMAMꢀ(DCNTH[4]):
ꢀ
DMAꢀsourceꢀdataꢀbankꢀregisterꢀ(DMRꢀworksꢀonlyꢀwhenꢀDMSꢀisꢀinꢀtheꢀrangeꢀfromꢀ8000hꢀtoꢀFFFFh).ꢀ
ꢀDMAꢀdestinationꢀaddressꢀincreasingꢀmodeꢀselectionꢀbitꢀ
0ꢀ=ꢀDestinationꢀaddressꢀincreasesꢀautomatically.ꢀ
1ꢀ=ꢀDestinationꢀaddressꢀisꢀfixed.ꢀ
ꢀ
ꢀ
TheꢀDMAꢀalwaysꢀmoveꢀ(DCNT+1)ꢀbytesꢀofꢀdata.ꢀDMAꢀwillꢀ
startꢀrightꢀafterꢀCPUꢀwriteꢀdataꢀintoꢀregisterꢀDCNTL.ꢀDuringꢀ
theꢀDMAꢀoperation,ꢀtheꢀCPUꢀhold,ꢀuntilꢀtheꢀDMAꢀtransferꢀ
completed.ꢀTheꢀDMRꢀregisterꢀresetꢀtoꢀ“$00”ꢀonꢀrealꢀchip,ꢀ
butꢀEmulationꢀBoardꢀisꢀ“unknown”,ꢀsoꢀrecommendꢀinitialꢀ
DMRꢀregisterꢀbeforeꢀuse.ꢀBefore Read/Write you have to
initial the PRR, DRR, DMR register when system reset.
ꢀ
Verꢀ2.5ꢀ
57
/75
ꢀ
9/16/2008ꢀ
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