SiI 1161 PanelLink Receiver
Data Sheet
Q
DE
VSYNC
HSYNC
TCK2OUT = max
50%
TCK2OUT= min
THD
TSU
RCIP
T
DUTY= max
TDUTY= min
ODCK
(OCK_INV=0)
50%
Figure 10. Receiver Clock-to-Output Delay and Duty Cycle Limits
TCLKPD
RXC+
..
QE[23:0], QO[23:0],
DE, CTL[3:1]
VSYNC, HSYNC
.
..
.
Figure 11. Output Signals Disabled Timing from Clock Inactive
TCLKPU + TFSC
RXC+
SCDT
Figure 12. Wake-Up on Clock Detect
SiI-DS-0096-D
16